This invention relates to transistors and capacitors in metal-oxide-semiconductor (MOS) structures, and in particular, a combined multi-finger power transistor and interdigitated multilayer (IM) capacitor structure in a deep sub-micron complementary MOS (CMOS) where the source and drain conductive lines are interconnected in multiple levels through vias to construct a parallel array of interdigitated vertical capacitor plates.
Power transistors in Class E power amplifiers operate as switches, periodically turning on and off at a desired operating frequency. Such amplifiers require a parallel capacitance (Cp) at the transistor""s output in order to shape the voltage and current waveforms. See F. Raab, xe2x80x9cIdealized Operation of the Class E Tuned Power Amplifierxe2x80x9d, IEEE Trans. Circuits and Systems, Vol. CAS-24, No. 12, December 1977, pp. 725-735.
FIG. 1A illustrates a simplified cross-sectional view of a typical N-channel (NMOS) power transistor 10 in Class E power amplifiers. The transistor is a xe2x80x9cmulti-fingerxe2x80x9d device having a plurality of N+ regions 12 diffused into a P-semiconductor substrate 11, such as silicon, these regions 12 forming alternating source and drain regions. A gate oxide layer 13, formed of an insulative material such as silicon dioxide (in the case of a silicon substrate), lies between the N+ source and drain regions 12 on the substrate 11. The gate oxide layer 13 serves as insulation between a metal gate 14 and the substrate 11. Source and drain contacts 15 and conductive lines 16 facilitate electrical interconnection of the transistor 10 to other structures. FIG. 1B is a circuit diagram illustrating this power transistor.
Class E power amplifiers have been shown to be capable of operating in the 1-2 GHz range for Wireless applications. See T. Sowlati et al., xe2x80x9cLow Voltage, High Efficiency Class E GaAs Power Amplifiers for Wireless Communicationsxe2x80x9d, IEEE. JSSC, October 1995, pp. 1074-1074; and T. Sowlati et al., xe2x80x9c1.8 GHz Class E Power Amplifier for Wireless Communicationsxe2x80x9d, Electronics Letters, Vol. 32, No. 20, September 1996, pp. 1846-1846.
Recently, the use of Class E amplifiers has been reported in sub-micron CMOS technology. See K. Tsai et al., xe2x80x9c1.9 GHz 1W CMOS Class E Power Amplifier for Wireless Communicationsxe2x80x9d, ESSCIRC, Proceedings, September 1998, pp. 76-79.
Providing a capacitance at the output of the power transistor in a Class E power amplifier is conventionally accomplished with a discrete and separate capacitor structure, wherein the parasitic capacitance associated with the transistor is extracted and counted as part of the capacitance. The capacitor is typically implemented with a conventional parallel plate capacitor structure.
The use of a separate capacitor structure has some disadvantages. In integrated circuit applications, a capacitor component undesirably enlarges the area of the circuit. Such area enlargements increase the cost of the circuit. Capacitors used in discrete/hybrid module applications, are provided xe2x80x9coff-chipxe2x80x9d and, therefore, must be wire-bonded to a discrete power transistor. For wireless applications in the GHz frequency range, the inductance of the wire-bonds cannot be ignored as it undesirably limits the functionality of the capacitor in shaping the voltage and current waveforms of the transistor.
Another disadvantage associated with the capacitors used conventional Class E amplifiers in sub-micron CMOS technology is that their conventional parallel plate structures are not scaleable. Therefore, as geometries scale down in deep sub-micron CMOS processes, the capacitance densities of these capacitors remain generally the same.
Interdigitated capacitors are used in microwave applications. These capacitors have closely placed, laterally interdigitated conductive line structures which generate fringing and cross-over capacitances. However, the cross-over capacitance produced by such capacitors is limited to a single conductor level.
Accordingly, there is a need for an improved capacitor structure for shaping the voltage and current waveforms of power transistors in deep sub-micron CMOS.
A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.